1. Field of the Invention
The present invention relates to programming of a multiprocessor system in order to support concurrent invocations of a program on respective processors in the system.
2. Background Art
With the advent of cache memory, there has been an advantage to coupling multiple processors to a shared memory for general-purpose applications. By providing a dedicated cache memory for each processor, each processor can operate at nearly 100% of the time by accessing cache memory most of the time and accessing the shared memory during a small percentage of the time. The shared memory can also be used for communication between the processors.
Since the introduction of the Intel PENTIUM (Trademark) microprocessor, the caches and memory management circuitry have been integrated onto commodity processor chips together with special machine instructions to facilitate the construction of multiprocessor systems. More recently, the cost of these commodity processor chips has dropped relative to the cost of other computer system components so that general-purpose systems using commodity processors can be expanded at reasonable incremental cost by substituting multiple processor circuit boards where single processor circuit boards were previously used. Memory management and initialization techniques for the Intel Pentium(copyright) microprocessor, including a programming example of switching from a real-dress mode to a protected address mode, are further described in the Intel Pentium(copyright) Processor Family Developer""s Manual, Vol. 3: Architecture and Programming Manual, 1995, pp. 11-1 to 11-25, 14-1 to 14-13, and 16-1 to 16-31.
One application for a multiprocessor system is a network server. A conventional operating system for a network server is the Unix system. The problem of converting the Unix system for execution on a multiprocessor architecture is discussed in H. S. Raizen and S. C. Schwarm, xe2x80x9cBuilding a Semi-Loosely Coupled Multiprocessor System Based on Network Process Extension,xe2x80x9d 1991 USENIX Symposium on Experiences with Distributed and Multiprocessor Systems. Operating system functions previously restricted to a single processor (such as shared memory, semaphores, message queues and symbolic links) need to be made safe for access by multiple processors. This normally involves the use of special instructions in the processor, such as the xchg instruction on the Intel Pentiumg Processor Family. These special instructions have a significant detrimental impact on the system performance. The detrimental impact is increased as more processors are added to the system.
In accordance with one aspect of the present invention, there is provided a method of operating a multiprocessor system. The multiprocessor system includes at least a first processor, a second processor, and a memory linked to each of the processors for read and write access to the memory by each of the processors. Each of the processors has an address translator for translating logical addresses specified by program instructions to corresponding physical addresses for addressing the memory. The address translator of the first processor accesses a first translation table, and the address translator of the second processor accesses a second translation table. The method includes allocating at least three non-overlapping regions in physical address space of the memory including a program region containing a program, a first data region for private read-write access by the first processor, and a second data region for private read-write access by the second processor. The method further includes initializing a first copy of program data in the first data region of the memory, and initializing a second copy of the program data in the second data region of the memory. The method further includes setting entries in the first translation table and in the second translation table so that each of the processors translates logical instruction addresses of program instructions of the program in the memory to physical addresses of the program instructions in the program region of the memory so that the processors share read-only access to the program in the memory during concurrent invocations of the program in the memory, so that the first processor translates logical data addresses specified by read-write access instructions in the program to physical addresses in the first data region of the memory, and so that the second processor translates the logical data addresses specified by the read-write access instructions in the program to physical addresses in the second data region of the memory. Moreover, the method includes each of the processors running concurrently a separate invocation of the program in the program region of the memory. Therefore, each of the processors can concurrently run a separate invocation of the program in a multiprocessor safe fashion without a substantial need for executing special multiprocessor instructions.
In accordance with another aspect, the invention provides a method of accessing a memory in a multiprocessor system including at least a first processor, and a second processor. The memory is linked to each of the processors for read and write access to the memory by each of the processors. Each of the processors has an address translator for translating logical addresses specified by program instructions to corresponding physical addresses for addressing the memory. The memory is accessed so that each of the processors may run concurrently a separate invocation of a program in a program region of the memory while accessing a shared data area in the memory. When using object oriented languages like C++, the startup of the program includes execution of a set of data initialization routines call constructors. These constructors would destroy the current state of the shared memory area if they were allowed to modify it during the startup of the second processor. Therefore, the method further includes copying shared data from the shared data area of the memory to a free area of the memory, the shared data area of the memory being referenced by constructors, changing address translation of the second processor from a first state to a second state so that the constructors reference the copy of the shared data, running the constructors so that the constructors access the copy of the shared data; and then returning the address translation of the second processor to the first state.
In accordance with yet another aspect, the invention provides a multiprocessor system comprising at least a first processor, a second processor, and a memory linked to each of the processors for read and write access to the memory by each of the processors. Each of the processors has an address translator for translating logical addresses specified by program instructions to corresponding physical addresses for addressing the memory. The address translator of the first processor is operative for accessing a first translation table, and the address translator of the second processor is operative for accessing a second translation table. The processors are programmed for allocating at least three non-overlapping regions in physical address space of the memory including a program region containing a program, a first data region for private read-write access by the first processor, and a second data region for private read-write access by the second processor. The processors are also programmed for initializing a first copy of program data in the first data region of the memory, and initializing a second copy of the program data in the second data region of the memory. The processors are also programmed for setting entries in the first translation table and in the second translation table so that each of the processors translates logical instruction addresses of program instructions of the program in the memory to physical addresses of the program instructions in the program region of the memory so that the processors share read-only access to the program in the memory during concurrent invocations of the program in the memory, so that the first processor translates logical data addresses specified by read-write access instructions in the program to physical addresses in the first data region of the memory, and so that the second processor translates the logical data addresses specified by the read-write access instructions in the program to physical addresses in the second data region of the memory. Moreover, the processors are programmed for each of the processors running concurrently a separate invocation of the program in the program region of the memory. Therefore, each of the processors can concurrently run a separate invocation of the program in a multiprocessor safe fashion without a substantial need for executing special multiprocessor instructions.
In accordance with still another aspect, the invention provides a multiprocessor system including at least a first processor, a second processor, and a memory linked to each of the processors for read and write access to the memory by each of the processors. Each of the processors has an address translator for translating logical addresses specified by program instructions to corresponding physical addresses for addressing the memory. Each of the processors is programmed for concurrently running a separate invocation of a program in a program region of the memory and accessing a shared data area in the memory. When using object oriented languages like C++, the startup of the program includes execution of a set of data initialization routines call constructors. These constructors would destroy the current state of the shared memory area if they were allowed to modify it during the startup of the second processor. Therefore, the second processor is further programmed for copying shared data from the shared data area of the memory to a free area of the memory that is referenced by constructors, changing address translation of the second processor from a first state to a second state so that the constructors reference the copy of the shared data, running the constructors so that the constructors access the copy of the shared data, and then returning the address translation of the second processor to the first state.